Field
The present disclosure relates to a display apparatus and a method of manufacturing the same and more particularly, to a display apparatus and a method of manufacturing the display apparatus which is improved in driving defect and process defect by forming a planarization layer on a pad area to have a different thickness from that of a planarization layer on a display area using a mask including at least one semi-transparent area.
Description of the Related Art
A display apparatus is configured to display images. The display apparatus can be implemented in various manners such as liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), vacuum fluorescent display (VFD), and organic light emitting display (OLED). Further, with the development of the information society, various demands for display apparatuses have been increasing. Accordingly, studies are being continuously conducted to apply the display apparatus to various devices, such as televisions, mobile devices, notebook computers, vehicles, and watches, in various manners.
A display apparatus includes at least one thin film transistor (TFT) for driving a pixel in a display area. Further, the display apparatus includes a plurality of pads, which can be connected to an external circuit, in a non-display area in order to transfer various signals to the TFT and the pixel.
The TFT and the pad can be formed through a semiconductor processor. For example, layers constituting the TFT and the pad may be formed through exposing, developing, and etching processes using a mask. Herein, while the TFT or the pad is formed, the etching process is performed many times. Therefore, various problems may occur. Specifically, while the TFT or the pad including a plurality of layers is formed, layers or electrodes constituting the TFT or the pad or a contact hole connecting layers may be damaged by the etching process which is performed many times. Details thereof will be described with reference to FIG. 1, FIG. 2A, and FIG. 2B.
FIG. 1 is a cross-sectional view provided to explain a typical display apparatus 10 and a method of manufacturing the same.
A substrate 1 of the display apparatus 10 includes a display area DA where images are displayed and at least one TFT is formed, and a non-display area where images are not displayed. Further, at least a part of the non-display area includes a pad area PA where a plurality of pads connected to an external circuit is formed. FIG. 1 illustrates only the display area DA where the TFT is formed and the pad area PA where the plurality of pads is formed for convenience in explanation. The TFT includes an active layer 2, a gate electrode 4, a source electrode, and a drain electrode. The pad includes a pad electrode 5 connected to the external circuit. FIG. 1 illustrates a step before the source electrode and the drain electrode are formed during a process of forming the TFT and the pad. Therefore, in FIG. 1, the source electrode and the drain electrode of the TFT are not illustrated.
The TFT and the pad illustrated in FIG. 1 can be formed in the display area DA and the pad area PA, respectively, at the same time through the same process in order to increase the efficiency of a manufacturing process. Specifically, the active layer 2 is formed in the display area DA of the substrate 1, and then a first insulation layer 3 is formed throughout the display area DA and the pad area PA. Then, the gate electrode 4 is formed on the first insulation layer 3 in the display area DA at the same time when the pad electrode 5 is formed on the first insulation layer 3 in the pad area PA. Then, a second insulation layer 6 is formed so as to cover the gate electrode 4 and the pad electrode 5. Thereafter, a planarization layer 7 is formed on the second insulation layer 6 in the display area DA. Then, a first contact hole CNT1 for exposing a part of the active layer 2 is formed in the planarization layer 7 and the second insulation layer 6 in the display area DA. At the same time, a second contact hole CNT2 for exposing a part of the pad electrode 5 is formed in the second insulation layer 6 in the pad area PA. The first contact hole CNT1 and the second contact hole CNT2 can be formed through a developing process to the planarization layer 7 and an etching process E to the first insulation layer 3 or the second insulation layer 6. Specifically, a portion of the planarization layer 7 corresponding to the first contact hole CNT1 may be removed through the developing process. Then, the first insulation layer 3 and the second insulation layer 6 corresponding to the first contact hole CNT1 in the display area DA and the second insulation layer 6 corresponding to the second contact hole CNT2 in the pad area PA may be removed through the etching process E.
In this case, while the first contact hole CNT1 and the second contact hole CNT2 are formed through the etching process E, the second insulation layer 6 in the pad area PA may be damaged. Specifically, if the etching process E is performed to form the first contact hole CNT1 and the second contact hole CNT2, the entire second insulation layer 6 in the pad area PA may be exposed to an etching material (or etchant). That is, as for the second insulation layer 6, not only a portion corresponding to the second contact hole CNT2 but also the entire second insulation layer 6 is exposed to the etchant. Therefore, an undesired portion of the second insulation layer 6 may be removed or a thickness of the second insulation layer 6 may be excessively reduced. Therefore, a surface of the pad electrode 5 may be damaged. If the surface of the pad electrode 5 is damaged, adhesion between the pad electrode 5 and the external circuit may be reduced. Accordingly, there may be an increase in driving defect of the display apparatus 10.
FIG. 2A and FIG. 2B are cross-sectional views provided to explain another typical display apparatus 20 and a method of manufacturing the same.
Referring to FIG. 2A, the planarization layer 7 is formed throughout the display area DA and the pad area PA. In this case, it is possible to reduce the above-described problem of damage to the second insulation layer 6 or the pad electrode 5 in the pad area PA caused by exposure of the entire second insulation layer 6 in the pad area PA to the etching material. However, while a planarization layer 7p in the pad area PA is removed, other problems may occur. Details thereof will be described below.
After the etching process E for forming the first contact hole CNT1 and the second contact hole CNT2, the planarization layer 7p in the pad area PA may not be removed. If so, while the external circuit is bonded to the pad electrode 5, there may be a contact error due to a large thickness of the planarization layer 7p. Therefore, after the first contact hole CNT1 and the second contact hole CNT2 are formed, the planarization layer 7p in the pad area PA needs to be removed.
Referring to FIG. 2B, the planarization layer 7p in the pad area PA may be removed through an ashing process A. The ashing process A refers to a process for decomposing or removing organic materials such as a photo resist residue or a polymer using oxygen (O2) and etc.
However, the problem is that while the planarization layer 7p in the pad area PA is removed, a size of the first contact hole CNT1 formed in the display area DA may be excessively increased. Specifically, the planarization layer 7 needs to be formed to a larger thickness than the insulation layers 3 and 6 in order to flatten upper parts of the plurality of layers disposed under the planarization layer 7. Herein, as the thickness of the planarization layer 7 is increased, a time for the ashing process A for removing the planarization layer 7p in the pad area PA may also be increased. If the ashing process A is continued for a long time, a planarization layer 7d in the display area DA may also be affected. That is, while the planarization layer 7p in the pad area PA is removed by the ashing process A, a part of the planarization layer 7d in the display area DA may also be removed. Thus, as illustrated in FIG. 2B, a size of the first contact hole CNT1 may be excessively increased, or a thickness of the planarization layer 7d in the display area DA may be smaller than a target value.
If the thickness of the planarization layer 7d in the display area DA is reduced, upper parts of the plurality of layers disposed under the planarization layer 7d may not be sufficiently flattened. Further, if the size of the first contact hole CNT1 is excessively greater than a design value, after the source or drain electrode connected to the active layer 2 is formed, an unnecessary space for the first contact hole CNT1 remains. Thus, additional defects may occur. For example, a structure such as a column spacer for maintain a cell gap of a liquid crystal layer included in the display apparatus 20 may be disposed in a peripheral area of the first contact hole CNT1 according to a design of the display apparatus 20. In this case, if a size of the first contact hole CNT1 is greater than a design value, a part of the structure may sink into the contact hole, and, thus, the structure may be out of alignment, which is called “gap error”. Further, a part of the pad electrode 5 exposed through the second contact hole CNT2 may be continuously exposed to oxygen (O2) and others during the ashing process A. Thus, the surface of the pad electrode 5 may be damaged, which may result in a decrease in adhesion between the pad electrode 5 and the external circuit.
In order to solve the above-described problems, the planarization layer 7 may be formed to have a larger thickness considering a margin of the planarization layer 7d in the display area DA which is removed by the ashing process A. However, in this case, the thickness of the planarization layer 7p in the pad area PA is also increased. Therefore, the ashing process needs to be performed for a longer time. As a process time or a time for the ashing process A is increased, the contact holes CNT1 and CNT2 may be further damaged. Accordingly, this may not be a fundamental solution.
The inventors of the present disclosure invented a display apparatus and a method of manufacturing the same. In the display apparatus, a structure of the planarization layer 7p in the pad area PA and a method of forming the same are optimized. Therefore, it is possible to suppress damage to the pad electrode 5 or the second insulation layer 6 during an etching process, and also possible to minimize damage to the contact holes CNT1 and CNT2 in the display area DA during the ashing process A.